This invention relates to a transistor circuit which comprises a plurality of insulated gate type complementary metal oxide semiconductor (CMOS) circuits and power source cells for driving these CMOS circuits.
Since the complementary metal oxide semiconductor (CMOS) circuit has the advantage that the circuit consumes only a very small amount of power in operation, the CMOS circuit can be suitably applied to a small size electronic device which is desirably to be operated with a small size cell such as an electronic wrist watch or electronic pocket calculator. The power consumption of the CMOS circuit is generally expressed by the following formula: EQU pd=.SIGMA.f.sub.n c.sub.n v.sub.n 2 (1)
where
f.sub.n : operation frequency in node n PA1 c.sub.n : capacity in node n PA1 v.sub.n : operation voltage in node n
For the requirement called for in designing the fundamental circuit arrangement and for the necessity for satisfying conditions necessary to obtain a desired or predetermined operation, the parameters such as f.sub.n and c.sub.n can not be arbitarily varied. Therefore, in order to minimize the power consumption of the CMOS circuit, it has been attempted to reduce the value of v.sub.n.
FIGS. 1a, 1b and 1c show prior art transistor circuits which have been known as being capable of attaining the above-mentioned purposes. In each of the prior art transistor circuits illustrated, one power source terminal of the CMOS circuit 1 is connected to one terminal of the cell 2 while the other power source terminal of the CMOS circuit 1 is connected to the other terminal of the cell 2 through a voltage-dropping element 3. In the transistor circuit in FIG. 1a, the voltage drop element 3 comprises a resistor and a smoothing capacitor in parallel connected to the resistor, in the transistor circuit in FIG. 1b, the voltage-dropping element comprises a diode and in the transistor circuit in FIG. 1c, the voltage-dropping element comprises a transistor. In the transistor circuit in FIG. 1c, the transistor is adapted to control the voltage drop amount across the two channels terminals in accordance with a control voltage applied to the gate of the transistor. In each of the three prior art transistor circuits illustrated, the voltage-dropping element 3 acts to reduce the current Ic flowing through the CMOS circuit in accordance with the voltage drop amount .DELTA.v to thereby realize reduction in power consumption in the CMOS circuit 1. However, since the voltage-dropping element 3 itself consumes an amount of power as represented by .DELTA.v.times.Ic, the power consumption saving effect of the overall transistor circuit is not appreciable.